Silo = VRAM (weights, KV cache)Elevator = memory bandwidthTiles = tokens, one per sackRed beacon = model does not fitA grain mill. The silo is GPU memory. The elevator is bandwidth: one lift per token. Each sack is a user, so batching is cheap. Watch the mill sit idle.To make one token the GPU must read every active weight out of VRAM once, so batch-1 decode runs at about 70% × bandwidth ÷ bytes per token, and the mill sits idle: an 8B model in BF16 on an RTX 5090 keeps its tensor cores busy about 1% of the time. Put more sacks under the chute and one lift serves them all: the weight read is shared, each user's KV cache is read again, and the mill gets busier until compute limits the step (the roofline ridge). Compute ceilings are NVIDIA's dense tensor figures for the format's math path (RTX Blackwell whitepaper; sparse AI TOPS ÷ 2 for FP4, ÷ 4 INT8, ÷ 8 FP8, ÷ 16 BF16 where only AI TOPS is published) at 50% efficiency; the M4 GPU is about 4.3 TFLOPS. In the drawing the belt speed is proportional to bandwidth and the whole machine runs 75× slower than real time: one lift (one decode step) every 75 × the seconds per token, so the counters count tiles and lifts in the drawing, while the dial on the scale shows the real total tokens per second. The sight glass is scaled to the card's capacity line; red above it is the overflow. When weights + KV cache + about 1 GB of runtime pass capacity, the model does not load: the gate shuts and the elevator stops (offloading to system RAM is Fig 9).